1. Design of AI Chip/Intelligent Computing Chip/Perception Analysis Chip

[1.1] L. Du, et.al,  A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 1, pp. 198-208, Jan. 2018 (IEEE CASS 2021 Darlington Best Paper Award)

[1.2] L. Du, et.al, A Reconfigurable 64-Dimension K-Means Clustering Accelerator with Adaptive Overflow Control, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 4, pp. 760-764, April 2020

[1.3] Y. Du, et al., An Analog Neural Network Computing Engine using CMOS-Compatible Charge-Trap-Transistor (CTT), in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 10, pp. 1811-1819, Oct. 2019

[1.4] K. Chen et al., A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5

[1.5] Y. Ma et al., In-Memory Computing: The Next-Generation AI Computing Paradigm. In Proceedings of 2020 on Great Lakes Symposium on VLSI (GLSVLSI '20). Association for Computing Machinery, New York, NY, USA, 265–270

[1.6] Z. Shao et al., Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression, in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2021.3120312.Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression | IEEE Journals & Magazine | IEEE Xplore

[1.7]Y. Xiao, W. Fan, Y. Du, L. Du and M. -C. F. Chang, CTT-based Non-Volatile Deep Neural Network Accelerator Design, 2021 18th International SoC Design Conference (ISOCC), 2021, pp. 258-259(https://ieeexplore.ieee.org/document/9613930)

2. Perception Algorithm Design

[2.1] R.Guo, et.al., “Better Transferability with Attribute Attention for Generalized Zero-Shot Learning” International Conference on Machine Learning(ICML)  Workshop on Human in the Loop Learning, June 2020

[2.2] M. Liu, et.al, Faster Human-Machine Collaboration Bounding Box Annotation Framework Based on Active Learning, International Conference on Machine Learning(ICML)Workshop on Human in the Loop Learning, June 2020

[2.3] M. Liu et al., Prototype-Voxel Contrastive Learning for LiDAR Point Cloud Panoptic Segmentation, IEEE International Conference on Robotics and Automation 2022.

3.Sensor chip design

[3.1] L. Du, et.al, A 2.3mW 11cm Range Bootstrapped and Correlated Double Sampling (BCDS) 3D Touch Sensor for Mobile Devices, IEEE International Solid-State Circuits Conference, pp. 122-123, Feb. 22-26, 2015

[3.2] L. Du, et.al, Airtouch: A Novel Single Layer 3D Touch Sensing System for Human/Mobile Device Interactions, ACM/IEEE Design Automation Conference, June 2016

[3.3] Y. Tang,  et.al, A Fully Integrated 28nm CMOS Dual Source Adaptive Thermoelectric and RF Energy Harvesting Circuit with 110mV Startup Voltage,  IEEE 2018 Custom Integrated Circuits Conference

4. High-speed interconnection and RF chip design

[4.1] Y. Du, et.al, A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection, in IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 1111-1122, April 2017

[4.2] J. Du, et.al, A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface, 2020 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2020

[4.3] Y. Kim et al., A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications, in IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1600-1612, June 2019

[4.4] S. Hao et al., An 8.3% Efficiency 96–134 GHz CMOS Frequency Doubler Using Distributed Amplifier and Nonlinear Transmission Line, 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2020

5.Internet of Things IoT/Financial Hardware Security Module Design/Others

[5.1] Y. Mei, et.al, A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security, 2020 33rd IEEE International System-on-Chip Conference (SOCC), Sep. 2020

[5.2] Y. Bai et al., An Efficient High-Throughput Structured-Light Depth Engine, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, doi: 10.1109/TVLSI.2022.3171854.https://ieeexplore.ieee.org/document/9772713