1. AI
芯片/智能计算芯片/感知分析芯片设计

[1.1] L. Du, et.al,  A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 1, pp. 198-208, Jan. 2018 IEEE电路与系统学会-CASS 2021年度最佳论文Darlington Best Paper Award

[1.2] L. Du, et.al, A Reconfigurable 64-Dimension K-Means Clustering Accelerator with Adaptive Overflow Control, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 4, pp. 760-764, April 2020

[1.3] Y. Du, et al., An Analog Neural Network Computing Engine using CMOS-Compatible Charge-Trap-Transistor (CTT), in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 10, pp. 1811-1819, Oct. 2019

[1.4] K. Chen et al., A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5

[1.5] Y. Ma et al., In-Memory Computing: The Next-Generation AI Computing Paradigm. In Proceedings of 2020 on Great Lakes Symposium on VLSI (GLSVLSI '20). Association for Computing Machinery, New York, NY, USA, 265–270

[1.6] Z. Shao et al., Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression, in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2021.3120312.https://ieeexplore.ieee.org/document/9585319

[1.7] Y. Xiao, W. Fan, Y. Du, L. Du and M. -C. F. Chang, CTT-based Non-Volatile Deep Neural Network Accelerator Design, 2021 18th International SoC Design Conference (ISOCC), 2021, pp. 258-259(https://ieeexplore.ieee.org/document/9613930)

[1.8] Y. Du, L. Du, W. Fan, Y. Xiao and M. -C. F. Chang, Characterization of Programmable Charge-Trap Transistors (CTTs) in Standard 28-nm CMOS for Nonvolatile Memory and Analog Arithmetic Applications, in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 7, no. 1, pp. 10-17, June 2021, doi: 10.1109/JXCDC.2021.3098469.(https://ieeexplore.ieee.org/document/9490647)

[1.9] S. Lu, J. Lu, J. Lin, Z. Wang and L. Du, A Low-Latency and Low-Complexity Hardware Architecture for CTC Beam Search Decoding, 2019 IEEE International Workshop on Signal Processing Systems (SiPS), Nanjing, China, 2019, pp. 352-357, doi: 10.1109/SiPS47522.2019.9020324.

[1.10] M. Wang, J. Mo, J. Lin, Z. Wang and L. Du, DynExit: A Dynamic Early-Exit Strategy for Deep Residual Networks, 2019 IEEE International Workshop on Signal Processing Systems (SiPS), Nanjing, China, 2019, pp. 178-183, doi: 10.1109/SiPS47522.2019.9020551.

[1.11] W. Liu, X. Wen, J. Lin, Z. Wang and L. Du, EAGLE: Exploiting Essential Address in Both Weight and Activation to Accelerate CNN Computing, 2019 IEEE International Workshop on Signal Processing Systems (SiPS), Nanjing, China, 2019, pp. 73-78, doi: 10.1109/SiPS47522.2019.9020555.

[1.12] Yufei Ma, Yuan Du, Li Du, Jun Lin, and Zhongfeng Wang. 2020. In-Memory Computing: The Next-Generation AI Computing Paradigm. In Proceedings of the 2020 on Great Lakes Symposium on VLSI (GLSVLSI '20). Association for Computing Machinery, New York, NY, USA, 265–270. https://doi.org/10.1145/3386263.3407588

[1.13] J. Zhu et al., Flexible-width Bit-level Compressor for Convolutional Neural Network, 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems (AICAS), Washington DC, DC, USA, 2021, pp. 1-4, doi: 10.1109/AICAS51828.2021.9458411.

 [1.14] Y. Huang et al., LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator, 2021 18th International SoC Design Conference (ISOCC), Jeju Island, Korea, Republic of, 2021, pp. 256-257, doi: 10.1109/ISOCC53507.2021.9613969.

[1.15] C. Xie et al., Deep Neural Network Interlayer Feature Map Compression Based on Least-Squares Fitting, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 3398-3402, doi: 10.1109/ISCAS48785.2022.9937412.

[1.16] X. Hu, Z. Shao, C. Xie, L. Du and Y. Du, SVR: A Shard-aware Vertex Reordering Method for Efficient GNN Execution and Memory Access, 2022 19th International SoC Design Conference (ISOCC), Gangneung-si, Korea, Republic of, 2022, pp. 165-166, doi: 10.1109/ISOCC56007.2022.10031440.

[1.17] W. Fan, Y. Li, L. Du, L. Li and Y. Du, A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-approximation and Single-slope Stages for Computing in Memory, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 3393-3397, doi: 10.1109/ISCAS48785.2022.9937285.

 [1.18] H. Geng, X. Chen, N. Zhao, Y. Du and L. Du, QPA: A Quantization-Aware Piecewise Polynomial Approximation Methodology for Hardware-Efficient Implementations, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 7, pp. 931-944, July 2023, doi: 10.1109/TVLSI.2023.3277023.

[1.19] Y. Bai, Z. Shao, C. Zhang, A. Jiang, Y. Du and L. Du, Live Demonstration: An Efficient Neural Network Processor with Reduced Data Transmission and On-chip Shortcut Mapping, 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, 2023, pp. 1-2, doi: 10.1109/AICAS57966.2023.10168666.

[1.20] C. Xie, Z. Shao, N. Zhao, Y. Du and L. Du, An Efficient CNN Inference Accelerator Based on Intra- and Inter-Channel Feature Map Compression, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 9, pp. 3625-3638, Sept. 2023, doi: 10.1109/TCSI.2023.3287602.

[1.21] Y. Li, L. Du and Y. Du, A Column-Parallel Time-Interleaved SAR/SS ADC for Computing in Memory with 2-8bit Reconfigurable Resolution, 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, 2023, pp. 1-5, doi: 10.1109/AICAS57966.2023.10168604.

[1.22] H. Zhang et al., SSM-CIM: An Efficient CIM Macro Featuring Single-Step Multi-bit MAC Computation for CNN Edge Inference, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 11, pp. 4357-4368, Nov. 2023, doi: 10.1109/TCSI.2023.3301814.

[1.23] H. Zhang, Y. Du and L. Du, Linearity Analysis for Charge Domain In-memory Computing, 2023 IEEE 15th International Conference on ASIC (ASICON), Nanjing, China, 2023, pp. 1-42023 15thIEEEInternationalConference on ASIC最佳论文奖)

[1.24] Y. Bai, Y. Li, H. Zhang, A. Jiang, Y. Du and L. Du, A Compilation Framework for SRAM Computing-in-Memory Systems With Optimized Weight Mapping and Error Correction, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2024.3366025

[1.25] W. Li, X. Chen, L. Du and Y. Du, A Strong-Arm Comparator Layout Design with Combined Expert Knowledge and Intelligent Optimization Algorithm in 65nm CMOS, 2023 8th International Conference on Integrated Circuits and Microsystems (ICICM), Nanjing, China, 2023, pp. 452-456, doi: 10.1109/ICICM59499.2023.10365798.

[1.26]Yichuan Bai, Xiaopeng Zhang, Qian Wang, Jingjing Lv, Lei Chen, Yuan Du, Li DuAn Area-Efficient CNN Accelerator Supporting Global Average Pooling with Arbitrary ShapesAICAS(已接收)

[1.27]Z. Shao et al., An Efficient GCN Accelerator Based on Workload Reorganization and Feature Reduction, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 2, pp. 646-659, Feb. 2024, doi: 10.1109/TCSI.2023.3343515.

2. 人工智能算法

[2.1] R.Guo, et.al., “Better Transferability with Attribute Attention for Generalized Zero-Shot Learning” International Conference on Machine Learning(ICML)  Workshop on Human in the Loop Learning, June 2020

[2.2] M. Liu, et.al, Faster Human-Machine Collaboration Bounding Box Annotation Framework Based on Active Learning, International Conference on Machine Learning(ICML)Workshop on Human in the Loop Learning, June 2020

[2.3] M. Liu et al., Prototype-Voxel Contrastive Learning for LiDAR Point Cloud Panoptic Segmentation, 2022 International Conference on Robotics and Automation (ICRA), Philadelphia, PA, USA, 2022, pp. 9243-9250, doi:

[2.4] Yijiang Liu, Huanrui Yang, Zhen Dong, Kurt Keutzer, Li Du, Shanghang Zhang, NoisyQuant: Noisy Bias-Enhanced Post-Training Activation Quantization for Vision Transformers, IEEE CVPR, 2023.( https://openaccess.thecvf.com/content/CVPR2023/papers/Liu_NoisyQuant_Noisy_Bias-Enhanced_Post-Training_Activation_Quantization_for_Vision_Transformers_CVPR_2023_paper.pdf)

[2.5] Xiao, Lirui, et al. CSQ: Growing Mixed-Precision Quantization Scheme with Bi-level Continuous Sparsification. Design Automation Conference (DAC) 2023.(https://ieeexplore.ieee.org/document/10247982)

[2.6] J. Lu et al., Training Deep Neural Networks Using Posit Number System, 2019 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, 2019, pp. 62-67, doi: 10.1109/SOCC46988.2019.1570558530.

[2.7] J. Lu et al., Training Deep Neural Networks Using Posit Number System, 2019 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, 2019, pp. 62-67https://ieeexplore.ieee.org/document/9088105

[2.8] J. Li et al., Grand Challenge on Software and Hardware Co-Optimization for E-Commerce Recommendation System, 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, 2023, pp. 1-5, doi: 10.1109/AICAS57966.2023.10168648.

[2.9] J. Li, Y. Du and L. Du, Siamese Network Representation for Active Learning, 2023 IEEE International Conference on Image Processing (ICIP), Kuala Lumpur, Malaysia, 2023, pp. 131-135, doi: 10.1109/ICIP49359.2023.10222798.

[2.10] J. Li et al., BEV-LGKD: A Unified LiDAR-Guided Knowledge Distillation Framework for Multi-View BEV 3D Object Detection, in IEEE Transactions on Intelligent Vehicles, doi: 10.1109/TIV.2023.3319430.

[2.11]C. Xie, Z. Shao, Z. Chen, Y. Du and L. Du, An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 4, pp. 782-786

[2.12]A. Jiang, L. Du and Y. Du, GroupQ: Group-Wise Quantization With Multi-Objective Optimization for CNN Accelerators, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2024.3363073

[2.13]Rongyu Zhang, Denis Gudovskiy, Yuan Du, Jiaming Liu, Yulin Luo, Yohei Nakata, Tomoyuki Okuno, Shanghang Zhang, Kurt Keutzer, Huanrui Yang, Zhen Dong (Feb 25 2024). Efficient Deweahter Mixture-of-Experts with Uncertainty-Aware Feature-Wise Linear Modulation, AAAI 2024, Underline Science Inc. DOI: 10.48448/d32a-tp25.

[2.14]Liulu He, Yufei Zhao, Rui Gao, Yuan Du, Li DuSFC: Achieve Accurate Fast Convolution under Low-precision ArithmeticIntenational Conference on Machine Learning(ICML)(已接收)

3. 传感芯片设计

[3.1] L. Du, et.al, A 2.3mW 11cm Range Bootstrapped and Correlated Double Sampling (BCDS) 3D Touch Sensor for Mobile Devices, IEEE International Solid-State Circuits Conference, pp. 122-123, Feb. 22-26, 2015

[3.2] L. Du, et.al, Airtouch: A Novel Single Layer 3D Touch Sensing System for Human/Mobile Device Interactions, ACM/IEEE Design Automation Conference, June 2016

[3.3] Y. Tang,  et.al, A Fully Integrated 28nm CMOS Dual Source Adaptive Thermoelectric and RF Energy Harvesting Circuit with 110mV Startup Voltage,  IEEE 2018 Custom Integrated Circuits Conference

[3.4] Liu, C.; Du, Y.; Du, L. A Contactless Glucose Solution Concentration Measurement System Based on Improved High Accurate FMCW Radar Algorithm. Sensors 2022, 22, 4126. https://doi.org/10.3390/s22114126

[3.5] Zhang, Xulong, Zihao Cheng, Li Du, and Yuan Du. 2023. Progressive Classifier Mechanism for Bridge Expansion Joint Health Status Monitoring System Based on Acoustic Sensors Sensors 23, no. 11: 5090.

[3.6] Z. Chen, Y. Xiao, L. Du and Y. Du, Characterization of Charge-Trap-Transistor (CTT) Threshold Voltage Degradation and Differential-Pair-Based Memory Design, 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 2023, pp. 1-5, doi: 10.1109/ISCAS46773.2023.10182219.

[3.7] 徐志航徐永烨马同川杜力, & 杜源. (2023). 面向cmos图像传感器芯片的3d 芯粒(chiplet) 非接触互联技术电子与信息学报, 45(9), 3150-3156.

[3.8] Y. Lin, Y. Xiao, J. Lv, L. Du and Y. Du, A Dual-Mode Broadband Image Sensor Based on Graphene-CMOS Integration, 2023 IEEE 15th International Conference on ASIC (ASICON), Nanjing, China, 2023, pp. 1-4

4. 高速互联及射频芯片设计

[4.1] Y. Du, et.al, A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection, in IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 1111-1122, April 2017

[4.2] J. Du, et.al, A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface, 2020 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, 2020

[4.3] Y. Kim et al., A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications, in IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1600-1612, June 2019

[4.4] S. Hao et al., An 8.3% Efficiency 96–134 GHz CMOS Frequency Doubler Using Distributed Amplifier and Nonlinear Transmission Line, 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2020

[4.5] Q. Liu, L. Du and Y. Du, A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for High-Density Interconnects, in IEEE Journal of Solid-State Circuits, doi: 10.1109/JSSC.2023.3261125.(https://ieeexplore.ieee.org/document/10090936)

[4.6] C. Zhao, W. Fan, J. Lv, L. Du and Y. Du, An X-band Phase Detector Based on Quadrature Modulation in 28-nm CMOS, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022, pp. 3077-3081, doi: 10.1109/ISCAS48785.2022.9937765.

[4.7] X. He, Y. Wu, Y. Bai, J. Liu, L. Du and Y. Du, A Reconfigurable Design of Flexible-arbitrated Crossbar Interconnects in Multi-core SoC system, 2022 IEEE 15th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Penang, Malaysia, 2022, pp. 368-374, doi: 10.1109/MCSoC57363.2022.00064.

[4.8] T. Ma, Z. Xu, L. Du and Y. Du, Inductively-Coupled High-Speed Interconnects of 3D-Integrated CMOS Image Sensors, 2022 7th International Conference on Integrated Circuits and Microsystems (ICICM), Xi'an, China, 2022, pp. 534-538, doi: 10.1109/ICICM56102.2022.10011292.

[4.9] J. Lv, L. Du and Y. Du, A 31–46 GHz Dual-Core Class-C VCO Using Switchable Transformers in 28-nm CMOS, in IEEE Microwave and Wireless Technology Letters, vol. 33, no. 9, pp. 1341-1344, Sept. 2023, doi: 10.1109/LMWT.2023.3288408.

[4.10] Y. Wu, T. Li, Z. Shao, L. Du and Y. Du, An Efficient Design Framework for 2×2 CNN Accelerator Chiplet Cluster with SerDes Interconnects, 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, 2023, pp. 1-5, doi: 10.1109/AICAS57966.2023.10168573.

[4.11] H. Zhang, Y. Li, W. Yin, Y. Du and L. Du, Design and Analysis of a Nanosecond Burst-Mode CDR Using MATLAB/Simulink and Opti-System Co-Simulation, in IEEE Photonics Journal, vol. 15, no. 5, pp. 1-6, Oct. 2023, Art no. 7101406, doi: 10.1109/JPHOT.2023.3307687.

[4.12]J. Lv, L. Du and Y. Du, A W-band Phase-Locked Loop with a Robust Injection-Locked Frequency Divider, 2023 8th International Conference on Integrated Circuits and Microsystems (ICICM), Nanjing, China, 2023, pp. 159-1632023 The 8th International Conference onIntegrated Circuits and Microsystems最佳论文奖)

[4.13]Jingjing Lv, Yajie Wu, Li Du, Yuan DuA wide locking range injectionlocked frequency divider with an autoadjusted injection bias[J]. Microwave and Optical Technology Letters, 2024, 66(2): e34071.

[4.14]Zhang P, Lv J, Hou S, et al. Near-Field Probing of Microwave Oscillators with Josephson Microscopy[J]. Nano Letters, 2024, 24(18): 5453-5459.

[4.15]X. Lu et al., A Non-Centralized Routing Scheme with Phase-Caching CDR for Nanosecond-Level Optical Switching Systems, 2023 IEEE 15th International Conference on ASIC (ASICON), Nanjing, China, 2023, pp. 1-4

5. 物联网IoT/金融硬件安全模块设计/其他

[5.1] Y. Mei, et.al, A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security, 2020 33rd IEEE International System-on-Chip Conference (SOCC), Sep. 2020

[5.2] Y. Bai et al., An Efficient High-Throughput Structured-Light Depth Engine, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, doi:10.1109/TVLSI.2022.3171854.https://ieeexplore.ieee.org/document/9772713

[5.3] Shui, H.; Geng, H.; Li, Q.; Du, L.; Du, Y. A Low-Power High-Accuracy Urban Waterlogging Depth Sensor Based on Millimeter-Wave FMCW Radar. Sensors 2022, 22, 1236.

[5.4] X. He, Y. Bai, Y. Liu, L. Du, Z. Wang and Y. Du, Low latency PAE: Permutation-Based Address Encryption Hardware Engine for IoT Real-Time Memory Protection, in IEEE Internet of Things Journal, doi: 10.1109/JIOT.2023.3333203.