Lightweight Memory Address Encryption IP

Technical introduction:

1. Project overview (research background + project overview)

    Memory security is an important topic in the field of smart devices and mobile terminals. In order to protect sensitive information such as keys and private data in memory, encryption frameworks centered on data encryption algorithms are widely used. However, the data encryption algorithm has the limitations of complex hardware implementation, large storage requirements, long encryption period and high power consumption. The hardware address encryption technology takes the address port of the encrypted memory as the starting point, and realizes the bijective relationship between the plaintext address set and the ciphertext address set. The hardware address encryption structure has the characteristics of low encryption period, low area, low power consumption and high efficiency. It has strong flexibility and can effectively enhance the security of the pure data encryption structure. It can be widely used in small devices such as IoT devices and mobile embedded devices. Related technologies are supported by CCF-Ant Fund.

2. Key technologies (technical advantages and features) 

  lApplicable to scenarios combined with data encryption, providing security in both content and location dimensions for data in storage. 

  lThe plug-and-play address encryption module, the integration of the PAE module in the SoC platform hardly needs to modify the source code of other modules of the SoC, reducing the difficulty of project development.

  lThe PAE integrated by the TSMC 40nm process uses 0.826 thousand equivalent gates (Gate Equivalents, GE) to achieve a 193-bit key length. 

3. Cooperation Model: Technology Transfer, Authorization, Licensing 

4. Contact us: hejing@nju.edu.cn

Fig.1 PAE address encryption module in SoC environment


文本框:TABLE IV  Security Parameters of Different Encryption Implementations  Encryption	Effective Key Length (bit)	Brute Force Attack Time  (cycles)  32-bit PAE	193	6.277×1057  32-bit GF-Enc	64	9.223×1018  3DES	192	1.569×1059  AES-128	128	3.403×1039  PRINCE [32]	128	1.701×1038  QARMA-128 [36]	128	1.701×1038  32-bit PAE+AES-128	321	4.486×1097

Fig.2 The main technical indicators of PAE address encryption