科研方向简介

高性能计算软硬件架构设计

面向人工智能算法，科学计算，光场成像等方向的高性能计算芯片设计。包括人工智能芯片，通用图形处理器计算芯片（GPGPU），存内/近存计算芯片，科学计算芯片，异构计算系统算法-硬件感知编译部署策略，高性能RISC-V计算核心。

ISCL高性能计算软硬件架构团队介绍

南京大学智能感知与通信实验室——高性能计算软硬件架构团队负责人为杜力老师，目前博士规模10名左右，硕士规模30名左右。每年在电路与系统领域高水平期刊和会议中发表多篇工作，并与国内外知名高校（清华，北大，圣母大学等）和企业（华为，大疆，平头哥，Intel中国，蚂蚁集团等）合作，为同学提供科研平台以及落地流片项目的参与机会。

欢迎有志于加入的同学提前与我们联系，相互了解，简历投递至以下邮箱，并注明“高性能计算软硬件架构团队”：

招生负责人：白一川博士ycbai@smail.nju.edu.cn

并抄送：杜老师ldu@nju.edu.cn 蒋老师jiangmingzhe@nju.edu.cn

想要加入攻读硕士的同学，我们期待这样的你：

1、掌握数字电路和数字IC相关基础知识，熟悉Verilog（或Systemverilog）编程以及计算机组成原理/体系结构更佳。

2、基本掌握软件编程（如C或C++）和基础数据结构知识。

3、具有良好团队意识，工作认真努力，勤于思考。

4、 特别优秀的同学予以单独考虑。

我们也欢迎优秀的本科/硕士同学加入到我们课题组攻读博士学位。

发表论文

(TC 2025) Yichuan Bai, Xiaopeng Zhang, Qian Wang, Yaqing Li, Yuan Du, Li Du: BE-NPU: A Bandwidth-Efficient Neural Processing Unit with Adaptive Processing Schemes for Reduced Off-Chip Bandwidth Demand.

(JSPS 2024) Yiping Shi, Mingyuan Ma, Sunan He, Yanfei Ren, Li Du, Yuan Du: Elimination of Non-Idealities for Multi-Channel Phased Array Systems with Zero-IF Receiver.

(IOTJ 2024) Xuewen He, Li Du, Yuan Du: Low-latency DAE: A Configurable Lightweight Hybrid Data and Address Encryption Engine for IoT Real-time NVM Protection.

(APCCAS 2024) Ning Zhao, Jiayuan Chen, Jingjing Lv, Chenjia Xie, Yuan Du, Li Du: A Streaming Transformer Accelerator with Efficient On-Chip Normalization.

(APCCAS 2024) Chengrui Li, Ning Zhao, Xiaopeng Zhang, Wei Gao, Chenjia Xie, Yuan Du, Li Du: An Efficient On-Chip Storage Solution for CNN Accelerator Based on Self-tuning and Co-scheduling.

(ICICM 2024) Xuewen He, Yaqing Li, Li Du, Yuan Du: A Configurable Real-Time Self-Test and Repair Engine for Improving the Reliability and Functional Safety of RAM Arrays.

(Electronics 2024) Junyong Hua, Hang Xu, Yuan Du, Li Du: Improved JPEG Lossless Compression for Compression of Intermediate Layers in Neural Networks Based on Compute-In-Memory.

(TVLSI 2024) Chenjia Xie, Zhuang Shao, Ning Zhao, Xingyuan Hu, Yuan Du, Li Du: A Fast-Convergence Near-Memory-Computing Accelerator for Solving Partial Differential Equations.

(AICAS 2024) Yichuan Bai, Xiaopeng Zhang, Qian Wang, Jingjing Lv, Lei Chen, Yuan Du, Li Du: An Area-Efficient CNN Accelerator Supporting Global Average Pooling with Arbitrary Shapes.

(TCAD 2024) Yichuan Bai, Yaqing Li, Heng Zhang, Aojie Jiang, Yuan Du, Li Du: A Compilation Framework for SRAM Computing-in-Memory Systems With Optimized Weight Mapping and Error Correction.

(TCAD 2024) Aojie Jiang, Li Du, Yuan Du: GroupQ: Group-Wise Quantization With Multi-Objective Optimization for CNN Accelerators.

(TCAS-I 2023) Zhuang Shao, Chenjia Xie, Zihan Ning, Qi Wu, Liang Chang, Yuan Du, Li Du: An efficient GCN accelerator based on workload reorganization and feature reduction.

(TVLSI 2023) Chenjia Xie, Zhuang Shao, Zhichao Chen, Yuan Du, Li Du: An energy-efficient spiking neural network accelerator based on spatio-temporal redundancy reduction.

(IOTJ 2023) Xuewen He, Yichuan Bai, Yujia Liu, Li Du, Zhongfeng Wang, Yuan Du: Low-Latency PAE: Permutation-Based Address Encryption Hardware Engine for IoT Real-Time Memory Protection.

(ASICON 2023) Hang Xu, Chenjia Xie, Xin Lu, Li Du, Yuan Du: Memory-Efficient Compression Based on Least-Squares Fitting in Convolutional Neural Network Accelerators.

(TCAS-I 2023) Chenjia Xie, Zhuang Shao, Ning Zhao, Yuan Du, Li Du: An efficient CNN inference accelerator based on intra-and inter-channel feature map compression.

(AICAS 2023) Yichuan Bai, Zhuang Shao, Chenshuo Zhang, Aojie Jiang, Yuan Du, Li Du:

Live Demonstration: An Efficient Neural Network Processor with Reduced Data Transmission and On-chip Shortcut Mapping.

(AICAS 2023) Yajie Wu, Tianze Li, Zhuang Shao, Li Du, Yuan Du: An Efficient Design Framework for 2× 2 CNN Accelerator Chiplet Cluster with SerDes Interconnects.

(TVLSI 2023) Haoran Geng, Xiaoliang Chen, Ning Zhao, Yuan Du, Li Du: QPA: A quantization-aware piecewise polynomial approximation methodology for hardware-efficient implementations.

(MCSoC 2022) Xuewen He, Yajie Wu, Yichuan Bai, Jie Liu, Li Du, Yuan Du: A Reconfigurable Design of Flexible-arbitrated Crossbar Interconnects in Multi-core SoC system.

(ISOCC 2022) Xingyuan Hu, Zhuang Shao, Chenjia Xie, Li Du, Yuan Du: SVR: A Shard-aware Vertex Reordering Method for Efficient GNN Execution and Memory Access.

(ISCAS 2022) Chenjia Xie, Zhuang Shao, Hang Xu, Xiaoliang Chen, Li Du, Yuan Du, Zhongfeng Wang: Deep Neural Network Interlayer Feature Map Compression Based on Least-Squares Fitting.

(TVLSI 2022) Yichuan Bai, Mingzhe Jiang, Qingyu Zhu, Xiaoliang Chen, Yuan Du, Li Du, Zhongfeng Wang: An Efficient High-Throughput Structured-Light Depth Engine.

(Sensors 2022) Hanyue Shui, Haoran Geng, Qiong Li, Li Du, Yuan Du: A Low-Power High-Accuracy Urban Waterlogging Depth Sensor Based on Millimeter-Wave FMCW Radar.

(TCAS-I 2021) Zhuang Shao, Xiaoliang Chen, Li Du, Lei Chen, Yuan Du, Wei Zhuang, Huadong Wei, Chenjia Xie, Zhongfeng Wang: Memory-efficient CNN accelerator based on interlayer feature map compression.

(ISOCC 2021) Yimin Huang, Kai Chen, Zhuang Shao, Yichuan Bai, Yafeng Huang, Yuan Du, Li Du, Zhongfeng Wang: LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator.

(AICAS 2021) Junhan Zhu, Xiaoliang Chen, Li Du, Haoran Geng, Yichuan Bai, Yuandong Li, Yuan Du, Zhongfeng Wang: Flexible-width Bit-level Compressor for Convolutional Neural Network

(ISCAS 2021) Kai Chen, Yimin Huang, Yuan Du, Zhuang Shao, Xingyu Gu, Li Du, Zhongfeng Wang: A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference.